Cadence Technology on Tour

오늘 있었던 시납시스 세미나에 이어, 케이던스 세미나 공고 입니다.

Synopsys 세미나는 회사 업무때문에 부득이하게 못갔습니다. UDF에 대한 이야기가 있었다고 하던데, 회사 후배들이 가서 자료만 좀 봤습니다.
케이던스도 역시 저전력에 힘을 기울이고 있죠? (format 전쟁중이기도 하구요 ^^; 아쉽게도 행정적인 문제로 IEEE 표준에서 약간 밀린 느낌이 있습니다만..)
관심있으신 분은 참석하세요..





  • 행사명 : Technology On Tour 2007
  • 일 시 : 2007년 5월 3일 (목) 09:00 ~ 17:00
  • 장 소 : 호텔롯데월드 3F 크리스탈볼룸
  • 주 최 : 케이던스코리아(유)



Tech Keynote :


[ Keynote title ] Power forward : Removing barriers to low power design and verifications


[ Speaker profile ] : Koorosh Nazifi


Koorosh Nazifi is the program director for the Power Forward Initiative within Cadence. He manages the development and delivery of all Power Forward related product support across Cadence Corporation. Previously, he program managed the Interoperability Initiatives within Cadence encompassing OpenAccess, OpenKit, and ECSM standardization. He has extensive engineering, marketing, and business development experience in the EDA and ATE markets, including marketing pioneering technologies in the field of low power RTL optimization and analysis starting in 1996. Previously, he has held engineering and marketing roles at Synopsys, Teradyne, and Schlumberger. He holds an MBA from San Francisco State University and a BS in mechanical engineering from University of Missouri in Rolla.


Keynote abstract


The ever increasing miniaturization and integration of voice, data, and video led by consumer electronics has brought low power management to the forefront of design challenges, no less equal to timing. Additionally, the ongoing trend toward shrinking process geometries and the power management complications resulting from increased device leakage has equally challenged designers and semiconductor manufacturers alike. The industry’s response has been development of optimization and implementation techniques such as multi-voltage supply domains, power shutoff, and dynamic voltage and frequency scaling coupled with new IP to address the increasing need for reduced energy consumption.


Much of these techniques are utilized at the physical implementation after the initial RTL design creation and exploration. The purpose of this talk is to define a new methodology that supports definition and capture of low power design intent at RTL to enable automation, flow efficiency and productivity gains while bridging the gap between design and verification due to limitations of HDL.



Functional Verification


[ Enterprise System-level Verification ]


Get an overview of the Incisive® Enterprise System-Level Verification Solution, which combines automated hardware, embedded software, and system-level verification with system-wide management and new high-performance engines. Combined with the Incisive Plan-to-Closure Methodology, the solution extends the capabilities of traditional ESL approaches, which focus only on systems engineers and C-level tools. Find out how this new approach enforces system requirements across all engineering functions including design and verification—from an abstract system-level model and verification plan to in-system IP verification, systems integration, validation, and system-level closure.


[ Incisive Plan-to-Closure Methodology ]


Get an overview of the Incisive® Enterprise System-Level Verification Solution, which combines automated hardware, embedded software, and system-level verification with system-wide management and new high-performance engines. Combined with the Incisive Plan-to-Closure Methodology, the solution extends the capabilities of traditional ESL approaches, which focus only on systems engineers and C-level tools. Find out how this new approach enforces system requirements across all engineering functions including design and verification—from an abstract system-level model and verification plan to in-system IP verification, systems integration, validation, and system-level closure.


[ Power-aware verification ]


Incisive Design Team Manager and Incisive Enterprise Manager can read the CPF and automatically extend the verification plan to include coverage analysis of power modes and power control signals, ensuring that all power-related logic is exercised completely during the verification process. Both products automate the tasks that would otherwise require intensive human interaction, custom-software development, or are simply impossible to achieve manually.



Digital IC design


[Cadence Low power solution]


Improve productivity, reduce risk, and achieve optimal trade-offs among timing, power, and area with the Cadence Low-Power Solution. See the industry’s first complete low-power solution, integrating design, verification, and implementation – enabled by Si2 Common Power Format (CPF).


[Encounter Conformal Constraint Designer]


See how CCD’s constraint check and exception generation integrated seamlessly in SOC Encounter environment.


[DFY flow]


See an overview of SoC Encounter GXL differentiated features – focused on high-end digital design at 65nm/45nm technology, and how these features address OCV, process defect challenges for fast design closure and minimum yield risk.



Custom IC design


[ IC 6.1 – Design environment / Simulation /  constraint flow ]


This demo focuses on the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment. You will discover some of the new features and functionality that are available, focusing on the enhanced productivity that designers enjoy with the introduction of assistance. You will also learn about the constraint management system that can be used to pass information the schematic through to layout.


[IC 6.1 – Layout suite / Constraint flow ]


Discover the new, common cockpit that integrates all the products designers can access at any time during the design. Learn how to quickly perform area estimation on a piece of data, obtain the information, and plug it into a floor planning technology. Alo see simple editing to correct violations, the use of pin placement technology, and design optimization.


[AMS/RF Kit – Building out wireless]


The Cadence® AMS Methodology Kit addresses analog/mixed-signal design challenges across some of today’s most competitive markets, including wireless, wired networking, and personal entertainment electronics. The Kit delivers a verified methodology, enabling IP, and consulting, all of which is demonstrated on an end-to-end mixed-signal design example.
The Cadence RF Design Methodology Kit helps shorten product development cycle time by increasing silicon predictability and enabling greater RF design productivity.



IC-PKG-PCB design / System-in-package design


[ RF/Digital SiP design & RF SiP Kit ]


Cadence system-in-package (SiP) design technology provides automation, integration, reliability and repeatability for system-level co-design, advanced packaging, and RF module design.


Cadence SiP solutions seamlessly integrate into Cadence Encounter® for die abstract co-design, Cadence Virtuoso® for RF module design, and Cadence Allegro® for package/board co-design.


[ Highspeed design (SI/PI/EMI challenges) ]


Whether you are designing PCB systems with large number of high-speed nets or a system with small number that operate in Multi-gigahertz (MGH) range, Allegro PCB SI offers a scalable, complete and integrated solution for SI engineers and hardware engineers to explore and resolve electrical performance-related issues at every stage of the high-speed PCB system design cycle.



[ Keynote title ] Cadence Logic Design Team Solution


[ Speaker profile ] : Yoon Kim


Yoon Kim is the Product Marketing Group Director at Cadence, responsible for defining and driving implementation of marketing strategies for various tools using formal verification technology. Prior to joining Cadence, Yoon has held engineering and management positions at Hewlett-Packard and LSI Logic, where she was involved in various ASIC and microprocessor designs and methodology development. Yoon holds a M.S. degree in electrical engineering from Stanford University and a B.S. degree in electrical engineering from MIT.


Keynote abstract


As designs increase in complexity and the impact of shrinking geometries on logic design grows, front-end design teams face an increasing number of challenges, many of which can put already tight schedules at risk. These challenges include the critical nature of power, a growing design/verification gap, logical physical effects, and others, and have up until today been tackled in a serial, ad-hoc and highly iterative manner. Together this all results in a schedule predictability crisis as the actual product development time can be twice as large, or more, as the expected schedule. As a result, logic design teams need a new method to effectively design, verify and implement their RTL block and chip-level designs-one that replaces today’s methods with a concurrent and highly predictable flow, without destabilizing existing design and verification processes. In this presentation we’ll provide a framework for addressing these problems



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2 thoughts on “Cadence Technology on Tour

  1. 1년에 한번은 이런데 가 줘야 쉬는 맛도 있고 좋은데… (더구나 이천이 아닌 서울에서)
    파트장이 잘 안 보내주려고 해요;;

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