등록은:  http://www.synopsys.com/news/events/sem ··· sem.html




≫ Primary Multi Track Agenda

Track A1 Abstract
Introduction to SystemVerilog testbench with the VMM Methodology
- Making the move from directed tests to constrained-random verification
- SystemVerilog testbench basics
- Strategies for adopting SystemVerilog testbench and the Verification Methodology Manual (VMM)

Debug and Analysis with DVE
- An overview of DVE (Discovery Visualization Environment)
- Using DVE for assertion, testbench and SystemC debug
- Using DVE with analog simulatioins

Track A2 Abstract
Formal Verification with Megellan
- Making the move from directed tests to constrained-random verification
- SystemVerilog testbench basics
- Strategies for adopting SystemVerilog testbench and the Verification Methodology Manual (VMM)

Verification of Low Power Designs
- An overview of DVE (Discovery Visualization Environment)
- Using DVE for assertion, testbench and SystemC debug
- Using DVE with analog simulatioins

Track B1 Abstract
Introduction to VMM Applications
- Register modeling and verification
- Block-to-system reuse and memory allocation techniques
- Data stream scoreboarding

Using Verification IP in a VMM Environment
- Using transaction-level SystemC models in a SystemVerilog environment
- Transaction-level Interface techniques in VCS
- Debugging mixed-abstraction, mixed-language environments in DVE

Track B2 Abstract
SystemC and SystemVerilog Design Verification with VCS
- Using transaction-level SystemC models in a SystemVerilog environment
- Transaction-level Interface techniques in VCS
- Debugging mixed-abstraction, mixed-language environments in DVE

Accelerating Verification using the VMM Hardware Abstraction Layer with ZeBu
- Introduction to hardware-assisted acceleration with the EVE ZeBu platform
- Using the VMM HAL to reuse a common testbench for simulation and acceleration
- Implementing acceleration-friendly checkers, monitors and data generators

Track C1 Abstract
Verifying Performance and Reliability of Nanometer Designs with HSIMplus
- Solutions for post-layout analysis with millions of extracted RC parasitics
- Verifying performance and reliability for IR drop effects and electromigration

Mixed-Signal Verification (MSV) challenges and solutions
- Bottom-up, mixed-signal Verification w/ Verilog, VHDL, & SPICE
- Mixed-language / Mixed-level simulation top down design and verification
- Transistor-level sign-off: why is this important?

Track C2 Abstract
Advanced high-accuracy circuit simulation with HSPICE
- Performing faster simulations
- Ensuring silicon accuracy with advanced models
- Improving productivity with behavioral modeling
- Employing high-speed signal integrity analysis capabilities
- Simulating process variability effects
- Accurately predicting PLL and VCO performance